The present invention relates to a semiconductor memory device and a method for fabricating the same and, more particularly, to a semiconductor memory device in which a logic region and a memory region having a diffusion wiring layer structure are embedded and to a method for fabricating the same.
As an electrically writable nonvolatile memory device, there has been known a semiconductor memory device having a structure (virtual ground system) in which a diffusion wiring layer using an impurity diffusion layer formed in a semiconductor substrate as wiring also serves as the source region or drain of a memory transistor.
As ultra-miniaturization, higher integration, higher performance, and higher reliability has been required of semiconductor memory devices in recent years, the semiconductor memory device having the virtual ground system described above has also been required to operate at a higher speed.
A conventional semiconductor memory device in which a memory region having the virtual ground system and a logic region are embedded is disclosed in, e.g., Japanese Laid-Open Patent Publication No. 2003-347511.
As shown in FIG. 2 in the patent publication mentioned above, a silicide layer 109 has been formed by using a salicide technology on the upper surface of the memory gate electrode 105 in a first active region 101 as the memory region, while a silicide layer 115 has been formed by using the salicide technology on the upper surface of each of a logic gate electrode 112 and an impurity diffusion layer 114 in a second active region 102 as the logic region.
However, as the miniaturization of a semiconductor device proceeds and design rules are reduced increasingly, the width of the gate electrode in the memory region is also reduced. Accordingly, a resistance value per unit length of the gate electrode (bar resistance) increases in proportion to the reciprocal of the gate width so that a resistance value per unit length (bar resistance) in a 0.1 μm process becomes ten times the resistance value per unit length in a 1 μm process. Even in a structure in which the upper surface of the gate electrode has been silicidized as in the conventional embodiment, a resistance value per unit length of a gate electrode (bar resistance) increases in proportion to the reciprocal of the gate width. If wires are further thinned, therefore, the structure in which the upper surface of the gate electrode is silicidized leads to the problem that it cannot satisfy both of the requirement for the ultra-miniaturization of a semiconductor device and the requirement for the higher-speed operation thereof. In a gate electrode in the virtual ground system, the dimension of the gate electrode perpendicular to the direction in which the gate electrode extends is termed the gate width.